Mie Fujitsu, CSEM to combine DDC, low voltage for IoT chips

April 21, 2016 // By Peter Clarke
Deeply Depleted Channel
Japanese chip manufacturer Mie Fujitsu Semiconductor Ltd. and Swiss research institute CSEM SA have agreed to collaborate on Deeply Depleted Channel (DDC) technology and near/sub-threshold voltage technology for integrated circuits aimed at the Internet of Things and wearables markets.

The goal of the partnership is to develop a best-in-class extreme-low power (ELP) platform for IC fabrication with the associated ecosystem to enable chip designs for energy-critical wearable and IOT devices. The platform is due to be ready for limited release in Q4 2016.

The agreement encompasses the development of ultra-low voltage standard cell libraries, power management cells and memories as well as the development of a demonstrator circuit to show the technology. The agreement also includes cross-licensing of related IP.

The agreement comes a year after Mie Fujitsu acquired the low-power CMOS technology using DDC transistors from the original developer SuVolta Inc. and that company was wound up (see What happened to: SuVolta? ). Both United Microelectronics Corp. and Fujitsu, the shareholders in Mie Fujitsu were licensees of the technology. CSEM, with origins that grew out of the Swiss watch industry, also has history in expertise in extremely low power electronic circuitry.

The team banking on the ability to combine the DDC method with low voltages to produce circuits with superior energy efficiency in relatively mature and low-cost process technologies such as 55nm and 40nm CMOS.

The DDC technology allows fabrication of low-leakage transistors operating at supply voltages (Vdd) below 0.5V to obtain superior power efficiency. The partnership claims dynamic power savings of up to 60 percent and static power savings of up to 98 percent.

Applying DDC to 40/55nm CMOS along with mixed-signal/RF and embedded non-volatile memory allows highly integrated analog and RF SoCs for IoT and wearable platforms.

The development is being conducted by way of direct collaboration between process engineers, library specialists and ULP design experts in Japan and Europe.

Related links and articles:

www.csem.ch

http://www.fujitsu.com/jp/group/mifs/en/

News articles:

What happened to: SuVolta?

SuVolta Power-Saving Chip Process Enters Production

UMC and SuVolta partner to develop 28-nm low-power process technology