Part of the CEVA-X family of multi-RAT multi-carrier PHY control processors, the CEVA-X4 leverages what the company claims to be the world's most efficient processor architecture for baseband applications, a unique implementation based on the company's brand new CEVA-X architecture framework.
The CEVA-X4 incorporates a unique set of baseband-optimized features and functions in a highly efficient manner. The 128-bit wide VLIW/SIMD processor features 8 MAC units in 4 identical Scalar Processing Units (SPUs) and a 10-stage pipeline, capable of running at 1.5GHz in 16nm and achieves 16 Giga operations per second.
The processor’s efficient control features include an integer pipeline, a complete 32-bit RISC ISA including hardware division and multiplication, and a Branch Target Buffer (BTB), achieving CoreMark / MHz score of 4.0, 60% better (per thread) compared to the most established in-house DSP used in smartphones today, according to CEVA.
For system control, the CEVA-X4 brings a holistic approach to modem design, utilizing the innovative CEVA-Connect technology to orchestrate the entire PHY system, comprising of DSPs, coprocessors, accelerators, memories and system interfaces.
It is equipped with dedicated hardware coprocessor interfaces and an automated data and control traffic management mechanism that eliminates any software intervention. Its memory subsystem supports an advanced non-blocking 2-way or 4-way caches with hardware and software pre-fetch capabilities.
Conceived as the company's internal design exploration tool to quickly churn out new devices on its roadmap, the CEVA-X architecture framework unifies control and DSP processing, bringing an innovative holistic approach to modem architecture to orchestrate DSPs, coprocessors, hardware accelerators, memories and system interfaces.
It features a scalable VLIW/SIMD architecture, up to 128-bit SIMD, a variable length pipeline and support for both fixed- and floating-point operations. The new CEVA-X is said to delivers 2X more DSP horsepower while consuming 50% less power than the previous generation CEVA-X. The architecture also includes a dedicated 32-bit zero-latency Instruction Set Architecture (ISA), 32-bit hardware division and multiplication, dynamic branch prediction and