The Voltus IC Power Integrity Solution, claims to deliver record performance and capacity power analysis to meet the needs of next-generation chip design. Cadence claims that Voltus is the industry’s first power integrity tool integrated with static timing analysis.
Voltus draws on new technology as well as integration with Cadence IC, package, PCB and system tools to enable design teams to better manage power issues throughout the product development cycle and achieve faster design closure.
The Voltus solution is aimed at speeding design signoff and closure and follows Cadence's release in May 2013 of the company's Tempus Timing Signoff Solution.
Voltus solution enables designers to shrink the critical power signoff closure and analysis phase to a minimum.
Voltus uses a hierarchical architecture that is capable of supporting large designs, and when coupled with the parallel execution, scales to multiple CPU cores and servers, enabling the analysis of designs of up to a billion instances. SPICE-accurate solver technology provides the most accurate power signoff results.
The Voltus analysis engine enables power calculation across the chip and addresses leakage, switching and internal power issues. The tool is also capable of carrying out power integrity analysis on the power grid by implementing IR-drop and electro migration checks.
Physically-aware power integrity optimization, such as early rail analysis, de-coupling cap and power gating switches, helps improve physical implementation quality and speeds up design closure. The tool is capable of focusing on power gating switch issues to provide designers with early power grid analysis during the floorplanning phase.
The Voltus IC Power Integrity Solution claims to provide even greater benefits when integrated with other Cadence tools. When used with the Tempus Timing Signoff Solution Cadence can offer the industry’s first unified electrical signoff solution for faster, converged timing and power signoff.
Many of the capabilities of Voltus are geared to tackle the design challenges posed by the increasing low power requirements of mobile devices