Both CEVA in Israel and Tensilica in the US have used customised instructions coupled with hardware accelerator blocks to provide the performance at acceptable power levels and are providing the IP to key customers now for shipping chips next year.
Tensilica says it has already secured lead customers for its new ConnX BBE32UE DSP IP core The core, coupled with Tensilica Baseband Dataplane processors (DPUs) provides a fully software programmable, flexible modem for LTE-Advanced user equipment category 7 PHY (Layer 1) with under 200 mW of power in TSMC’s 28 nm HPL process. The core can also support 2G, 3G, LTE and HSPA+ standards.
Data bandwidth is a key criteria for LTE-Advanced User Equipment applications and the ConnX BBE32UE uses dual 256-bit load/store units to reduce power. Additionally, designers can use Tensilica’s proprietary Port (general-purpose I/O) and Queue interfaces to directly connect hardware blocks to the processing ALUs. This allows single cycle dedicated access without the need to go over a system bus, hence reducing the required clock frequency and power consumption.
CEVA has also looked to expand the data bandwidth of its devices with a 2048bit wide interface from its core to the L1 data cache to tackle the same issues. Its CEVA-XC4000 is a series of six fully programmable DSP cores with a unified development infrastructure composed of code-compatible cores, a set of optimized software libraries and a single tool chain. It has also developed a new low latency interconnect to link the blocks.
“The CEVA-XC4000 redefines the concept of a ‘universal communication architecture’,” said Gideon Wertheizer, CEO of CEVA. “Incorporating new power management techniques, we were able to dramatically reduce the power consumption for high-performance software-based processing, paving the way for modem developers to exploit the flexibility, reusability and time-to-market advantages that a software-defined approach brings.”
CEVA has enhanced its second generation Power Scaling Unit (PSU 2.0) which dynamically supports clock and voltage scaling with fine granularity