The company , based on the Isle of Wight, has successfully extended the dynamic range of an 8bit 800MSPS ADC from 52dB up to 74dB (see figure) in order to meet specific customer requirements for an industrial test product design.
The dynamic range of the ADC was extended by employing a stacked ADC architecture. This approach provides large gains in dynamic range by use of parallel data capture paths with staggered attenuation settings. Matching the frequency, phase and amplitude characteristics on these parallel paths is critical to a successful implementation. Therefore special attention was focused on the architecture of the analogue design to mitigate potential mismatch of device characteristics.
The ADCs were supplied by e2V and the multi-channel analogue and digital design uses six, quad speed, EV8AQ160 ADCs, two 1.6GHz PLLs, four high speed FPGAs and a processor. The complexity of integrating multiple large BGA devices and associated high speed I/O into a small area required a 14-layer PCB design. The added signal sensitivity requirement necessitated linear power supply regulators, low noise analogue components and careful layout of power planes. Analogue simulation was used to prove the stability and frequency response of the input chain whilst the RTL design was checked against a bit true Matlab model.
After the received signal has been converted to the digital domain, the input data rate for each channel is 29Gb/s. Initial signal processing reduces the rate whilst maintaining full timing precision. Further time and frequency domain measurements are applied before passing results on to the processor. Software handles final adjustments to the data and manages the user interface and a network connection allows control, data transfer and updates to be carried out via remote access.
"Our many man-years of leading-edge, signal processing design knowledge enabled us to really push the envelope of the ADCs' dynamic range so that the customer could get a new product on the market that has 'best in class'