Built on a multi-threaded architecture (power analysis is parallelized across multiple CPUs accelerating in-depth power exploration), the register-transfer level (RTL) power analysis solution enables SoC design teams to analyze power consumption accurately during design exploration.
The Joules RTL Power Solution incorporates rapid prototype technology from the Cadence Genus™ Synthesis Solution engine and can analyze designs of up to 20 million instances overnight with gate-level accuracy within 15 percent of final power as signed off in the Cadence Voltus™ IC Power Integrity Solution, says the company.
The tool performs an ultra-fast design synthesis using a new integrated prototype mode of the Genus Synthesis Solution, including physically aware clock tree and datapath buffering, and enabling accurate RTL power estimation.
User-selectable frames can be used to zoom in on power-critical periods of the simulation, and multiple stimuli for different design hierarchies can be merged to mimic full SoC traffic and power consumption. This enables design teams to easily analyze critical power problems.
What's more, power can be reported at the bit level or register level and may be categorized based on logic cell type, design hierarchy, clock domain, power domain or timing mode. A rich suite of library analysis and profiling tools is also included.
The Joules RTL Power Solution can be used within the Palladium Dynamic Power Analysis for more accurate time-based power calculations. This provides enhanced production-correlated peak and average power analysis, enabling design teams to analyze system power of software running on hardware early in the development cycle.
The new solution is also integrated with the Stratus HLS platform for earlier and more accurate power estimates, enabling IP teams to better evaluate system-level micro-architectural tradeoffs.
For more information on the Joules RTL Power Solution, visit http://www.cadence.com/news/joules.
Cadence Design Systems GmbH at www.cadence.com