S3 claims smallest, most efficient 12bit SAR ADC, again

June 11, 2015 // By Peter Clarke
Intellectual property licensor S3 Group Ltd. (Dublin, Ireland) has doubled the sample frequency on the next member of its 12-bit SAR ADC core and targeted the design to 28nm CMOS.

This year's device samples at up to 320Msamples/s and is aimed at communication standards that are driving spatial diversity techniques, meaning greater numbers of high-performanc ADCs operating in parallel. That in turn puts increases the need to minimize power consumption in each ADC. The 320M/s follow on consumes about 10mW, and occupies 0.05 square millimeters of silicon in a 28nm manufacturing process.

Part of the Magellan family of ADCs from S3, this 320MS/s 12bit ADC targets highly integrated SoCs, such as those requiring next generation 802.11ac leading to 802.11ax connectivity in addition to next generation DSL connectivity. Available in 40nm and 28nm the convertor also delivers excellent dynamic linearity performance, S3 claims.

"Advanced communication standards in the cellular, WiFi and DSL segments, are incorporating spatial diversity techniques that lead to the inclusion of multiple ADCs on single SoCs. Equally as important as the challenge of delivering robust dynamic linearity at higher sample rates, is the need for smaller ADCs that consume less power." said Darren Hobbs, director of product management for semiconductor solutions at S3, in a statement.

Relared links and articles:

www.s3group.com

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