Perhaps the most relevant announcement is the development of a low-cost 14nm FinFET process, 14nm LPC. The company has already shipped more than half a million 14nm wafers and expanded the process to included networking/server and automotive applications, but Samsung’s Kelvin Low said he expects next-generation applications to move to the lower-cost option.
“There are always concerns about trading off cost versus performance,” Low, Samsung’s senior director of foundry marketing, told EE Times. “LPC has the same PDK of [14nm] LPP. The number of steps has been reduced…That allows us to achieve a lower cost point on manufacturing and we decide to share that with our customers.”
Samsung will also offer an RF add-on to 14LPC this year. Low wouldn’t elaborate on just what steps had been reduced, or discuss the cost differential between 14nm LPP (Low-Power Plus—the 2nd generation of the company’s 14nm FinFET process technology) and LPC processes. The lower-cost option will be available sometime this year.
Low added that Samsung will release a 10nm LPP process technology that offers a 10% performance boost from the first-generation 10nm LPE (Low-Power Early) process. Although the foundry has begun work on a 7LPP node with “competitive PPA scaling,” Low said there is confusion about 10nm and 7nm.
“We think 10nm will be a much longer node than other foundries are claiming it will be. We think 7nm has to be defined and optimized to be cost effective to the masses, not just the high margin products,” he said. “EUV is an important enabler for a 7m cost affordable node.”