A typical configuration of the eSi-32X0MP to address wireless/cellular standards comprises an asymmetric dual core processor. One processor is optimized for implementing physical layer (PHY) processing and the second core is optimized for running an advanced protocol stack.
However, the eSi-32X0MP can be configured with an unlimited number of processors depending on the application. Indeed, an early implementation already in production is a seven core eSi-3250MP for multi-gigabit packet processor acceleration.
The eSi-32X0MP's PHY core provides advanced DSP acceleration with dual-MAC and SIMD instructions for complex arithmetic as well as fast divide, square root and log calculation acceleration. The second core’s advanced protocol stack accelerates various bit field operations, such as fast insertion and extraction, and a cyclic redundancy checker (CRC).
The processor sub-systems can be enhanced for symbol level processing including FFT/IFFT, DFT, Viterbi and Turbo decoding using optional hardware accelerators from EnSilica's eSi-Comms IP library.
Security layers can be implemented with the aid of a memory protection unit (MPU), True random number generator (TRNG) and optional hardware accelerators for Snow3G, AES, RSA and ECC from EnSilica’s eSi-Crypto IP library.
For advanced power saving, the eSi-32X0MP implements both clock and power gating. Power gating is supported through a UPF-based (Universal Power Format) design compatible with standard front and back-end EDA tool flows. Load-locked and store-conditional instructions are provided to support inter-core communications. Both the processor and tool chain fully support multicore debug.
Each core can deliver up to 3.72 CoreMark per MHz and, when speed optimized in TSMC’s 28nm HPC process, can be clocked at over 1GHz with a dynamic power of only 14.4µW/MHz per core. When optimized for power the dynamic power for each core is only 5.09µW/MHz.
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