Si-CMOS compatible nanopillar LEDs promise accurate photonics integration

March 07, 2017 // By Julien Happich
Researchers from the University of California at Berkeley have not only demonstrated the design of III−V nanopillar LEDs with a Si-CMOS compatible optical lithography process, they also controlled the precise growth location of these nano LEDs, a key element for the effective integration of photonics into CMOS circuits for fast on-chip optical interconnects.

Published in the ACS Photonics journal under the title "Ultracompact Position-Controlled InP Nanopillar LEDs on Silicon with Bright Electroluminescence at Telecommunication Wavelengths", the article reports the site-controlled growth of high-yield (90%) uniform arrays of InP nanopillars on silicon, grown under CMOS compatible conditions: low temperature and without catalysts.

Tilt-view low magnification SEM images
of arrays of site-controlled InP nanopillars
grown at 460°C. The scale bar in all images
corresponds to 10 μm and the growth
periods (pitch) are 1 μm, 4 and 40μm,

The researchers started with a clean silicon wafer (111), depositing 140nm of silicon dioxide (at 350°C) into which they defined nanoscale apertures about 320nm in diameter to position the nanopillar nucleation sites, with a pitch varying from 1 to 40μm. After chemically roughening the silicon surface, the researchers grew the InP nanostructures in a MOCVD chamber at temperatures between 450 and 460°C. They found that the taper angle of the nanopillar was largely affected by growth temperature, yielding nanoneedles at 450°C but nearly vertical pillar-shaped structures at 460°C.

On the basis of these nanopillars and through a concentrical core−shell growth, the researchers incorporated five InGaAs quantum wells in the active region of a pn diode, forming electrically driven n-InP/InGaAs MQW/p-InP/p-InGaAs nano-LEDs.

Schematic of the nanopillar MQW LED device.