Sony stacks CMOS image sensor with DRAM: full HD readout at 1000fps

February 07, 2017 // By Julien Happich
Sony Corporation has developed what the company claims to be the industry's first 3-layer stacked CMOS image sensor with DRAM for smartphones.

The unit consists of a DRAM layer added to the conventional 2-layer stacked CMOS image sensor (back-illuminated structure pixels and a signal processing). Using a stacked solution, the company says it was able to speed up data readout, enabling the capture of still images of fast-moving subjects with minimal focal plane distortion, but also supporting super slow motion movies at up to 1,000 frames per second in full HD (1920x1080 pixels).


Conventional 2-layer stacked CMOS image sensor.

For the high-speed readout, the company doubled the circuit used to convert the analog video signal from pixels to a digital signal, from a 2-tier construction to a 4-tier construction, improving processing ability.


Newly developed 3-layer stacked CMOS image
sensor with DRAM.

Although there are speed limitations in the interface specifications for outputting signals from image sensors to other LSIs, this sensor uses DRAM to store signals read at high speed temporarily, enabling data to be output at an optimal speed for the standard specifications. As a result, the product is capable of reading one still image of 19.3 million pixels in only 1/120 of a second (approximately 4x faster than conventional products).

The new stack also solves various technical problems inherent in the design, reducing the noise generated between the circuits on each of the three layers.