SRAM IP operates below 0.7 volts on TSMC process

May 26, 2016 // By Peter Clarke
SureCore Ltd. (Sheffield. England) has developed low-voltage SRAM IP that has been proven in TSMC's 40ULP 40nm manufacturing process at voltages down to 0.6V.

This is the second product offering from SureCore, which was founded in 2011. It complements SRAM IP for the STMicroelectronics/Samsung 28nm fully depleted silicon-on-insulator (FDSOI) process that SureCore has offered for the last year (see SRAM IP available for FDSOI 28nm foundry processes ).

The design is based on the standard 6-transistor bit cell and scales with logic down to near-threshold operation. At 0.66V it is able to cut more than 90 percent of dynamic power consumption compared with standard foundry offerings that typically only operate down to 0.9V.


Paul Wells, CEO of SureCore Ltd.

Paul Wells, CEO of SureCore, told EE Times Europe that ULP process offerings claiming logic operation down to 0.7V or lower are essentially not viable without a suitable SRAM circuit that can operate at the same voltage. And this is something not available until now.

SRAM is usually the circuit most sensitive to voltage reduction as bit flip time extends with reduced voltage along with a susceptibility to bit-flipping on read, Wells said. SureCore's way round this problem is fairly straightforward, which is to include voltage boosting circuitry that operates only for the duration of a read or write. Wells calls it "smart assist" technology.

"These are capacitive boost circuits. But you do have to beware of overboosting," Wells said. At higher voltages the voltage boost is not required and the SRAM is characterized as operating from 1.1V down to 0.66V both +/- 10 percent. At higher voltages the memory is capable of operating at a clock frequency of 300MHz.

There is a die area and power consumption overhead to be paid for this functionality. Wells estimated the die area penalty at about 20 percent compared with a vanilla 6T-SRAM design.

The compiler yields memories ranging in capacity from 8kbits up to 576kbit and by use of memory banking in independently active, retained or powered off states it is possible to provide additional support for