SureCore SRAMs design-ready, says CEO

October 06, 2016 // By Peter Clarke
First tape-outs could come as soon as the first quarter of 2017 for memory intellectual property licensor SureCore Ltd. (Sheffield, England), according to company CEO, Paul Wells.

SureCore is ready to supply all the necessary materials to enable design-in of its SRAMs for both ST's 28nm FDSOI process and the 40ULP process from TSMC, he said.

The company has been developing its technology after being founded in 2011. Paul Wells, told EE Times Europe that to license IP successfully it is necessary to have silicon-proven design as multiple EDA views, models and libraries.

"We have a silicon evaluation report prepared on SRAM built on a TSMC shuttle run, which we are prepared to release under non-disclosure agreement. Everything is now in place – the compilers, the models, the characterization – to allow design-in," said Wells. "We are in evaluation with several potential customers for inclusion in real products," he added

Wells said first tape outs could come as soon as the first quarter of 2017.

SureCore is offering both low-power and single-port ultra-low voltage SRAMs

The low power SRAM IP products have been realized in both 28nm FDSOI and TSMC 40ULP manufacturing processes. It operates across a voltage range of 0.7 to 1.2V, The single-port ultra low voltage (ULV) SRAM IP is silicon-proven on TSMC’s 40ULP process and provides up to 80 percent savings in dynamic power consumption and an up to 75 percent reduction in static power. This memory operates down to a record-setting 0.6V across process, voltage and temperature delivering an impressive operating voltage range from 0.6V to 1.21V. It provides a 20MHz cycle time at 0.6V scaling to over 300MHz at 1.21V.

Earlier this year SureCore announced a Series B investment. Mercia led the $2 million investment alongside existing investors Finance Yorkshire Seedcorn Fund and Capital-E.

Related links and articles:

www.sure-core.com

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