Synchronous DC/DC controller maintains regulation in automotive start/stop systems

February 08, 2013 // By Paul Buckley
Linear Technology Corporation introduces the LTC3859AL, a triple output (buck, buck, boost), low quiescent current synchronous DC/DC controller that maintains all output voltages in regulation during automotive cold crank conditions.

A 12 V automotive battery can droop to less than 4 V during engine restart or cold crank, causing reset of infotainment systems and other electronics that operate from 5 V and higher. The high efficiency synchronous boost converter feeds the two step-down converters, avoiding output voltage dropout when the car battery droops, a useful feature in automotive start/stop systems that shut off the engine at idle to save fuel. Alternatively, the buck controllers can be powered from the input for a general purpose triple output controller.

The LTC3859AL operates from an input voltage of 4.5 V to 38 V during start-up and maintains operation down to 2.5 V after start-up. The synchronous boost converter can produce output voltages up to 60 V and can run at 0% duty cycle (synchronous switch ON) to pass through the input voltage when required to maximize efficiency. The two step-down converters can produce output voltages from 0.8 V to 24 V with the entire system achieving efficiency as high as 95%. In addition, the LTC3859AL can be configured for Burst Mode operation, reducing quiescent current to 28 µA per channel (38 µA for all three on) in sleep mode, a useful feature for preserving battery run-times.
The 1.1 Ohm onboard all N-channel gate drivers minimize MOSFET switching losses and provide an output current of more than 10 amps per channel, limited only by external components. Furthermore, the output current for each converter is sensed by monitoring the voltage drop across the inductor (DCR) or by using a separate sense resistor.

The LTC3859AL’s constant frequency current mode architecture enables a selectable frequency from 50 kHz to 900 kHz or it can be synchronized to an external clock with its internal phase-locked loop (PLL) from 75 kHz to 850 kHz.

Additional features include an onboard LDO for IC power and gate drive, output voltage tracking or adjustable soft start, a power good signal and an