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Synopsys touts ‘Visually Assisted Automation’ for FinFET design

Synopsys touts ‘Visually Assisted Automation’ for FinFET design

Technology News |
By Julien Happich



The incorporation of FinFETs—3D transistors—create significant challenges for designers, including increased design rule complexity, additional layers of interconnect and the need for the use of double-pattern lithography to produce them. Synopsys estimates that it takes about three times more effort to do a custom designed circuit with FinFETs than it would take to do an equivalent planar circuit, according to Dave Reed, director of marketing for Synopsys’ analog/mixed-signal design tool group.

”FinFET brings a significant challenge to custom design,” Reed said in an interview with EE Times.

Synopsys claims that the new tool, Custom Compiler, can reduce many tasks associated with custom design from days to a matter of hours. The tool is also said to reduce iterations of designs and help enable reuse.

According to Reed, Synopsys first became fully aware of the challenges posed by custom designs with FinFETs from the company’s team of intellectual property developers. “The nice thing about these folks is that because they are doing IP development, they are among the very earliest users of new nodes,” Reed said. “We have been doing a lot together, learning how to improve custom layout for FinFET designs.”

Custom Compiler bucks the trend in custom analog design tools of moving toward constraint-driven design methodologies. Rather than require designers to write code or constraints, Custom Compiler uses what Reed calls a visually-based, successive refinement approach.

”Visually assisted automation uses the natural language of a layout person, which is graphic manipulation,” Reed said. “We don’t make them write constraints, we don’t make them write code, and we don’t try to automate something by writing a complex array generator. Instead, we do our best to infer constraints from the work that the layout person is doing.”

Synopsys believes that constraint-based design has some real flaws that have prevented it from taking off, Reed said. While the idea behind the methodology makes sense for digital designs, he added.

Fig. 1: Synopsys says the growing number of FinFET design starts and tapeouts point to the need for a new custom design solution. Source: Synopsys.

”But in analog, we have a very complex set of constraints to describe what we really want to happen,” he said. “A lot of what happens is human intuition. Some of the things that we have to tell the tool are very complicated. What people have found is that by the time they got done editing the text constraints, they may as well have just done the layout themselves.”

The other problem with constraint based design is what Reed refers to as the “take it or leave it approach,” he said. Constraints are input into the tool and it spits out a design. And if the designer doesn’t like the solution, the only recourse is to go back in and edit the constraints, then push the button again. “People find that that’s not a real converging solution,” Reed said.

Reed stresses that Custom Compiler provides all the basic functionality that users are looking for. At its root, the tool is a layout editor and a schematic editor that provides “all the polygon-pushing and schematic features” that layout designers are accustomed to, he said. But on top of that, Custom Compiler provides visually assisted automation capabilities and “assistants” in four categories:

Layout assistants to provide visually guided automation of placement and routing; In-design assistants to reduce design iterations by catching physical and electrical errors before signoff; Template assistant to enable reuse by making it easy to apply previous layout decisions to new designs; and co-design assistants that combine Synopsys’ IC Compiler and Custom Compiler into a unified solution.

Reed said that while users do not need to deal with writing constraints, by using Custom Compiler they are actually creating constraints “under the covers” in a way that is transparent to them by noting how the user arrives at a solution and offering that same solution for reuse elsewhere in the design and in future designs.

Fig. 2: Block diagram overview of Custom Compiler, including integration with IC Compiler. Source: Synopsys.

”In analog design, everything is variations on a theme,” Reed said. “There are the same basic circuit types being used over and over and over again. We thought if there were a way for us to abstract that pattern of what the layout person had done and save it so they can reapply I later, that that would be a real time-saver.”

Reed said Synopsys has been using Custom Compiler internally since last summer. Several customers have been using the tool since late last year, he added. In support of the product’s release Wednesday, Synopsys announced that users include STMicroelectronics NV, GSI Technology Inc. and Asahi Kasei Microdevices Inc.

Synopsys also announced that Custom Compiler has been certified for Taiwan Semiconductor Manufacturing Co. Ltd.’s 10nm and 7nm process nodes.

 

About the author:

Dylan McGrath covers the semiconductor industry for EE Times – www.eetimes.com

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