The incorporation of FinFETs—3D transistors—create significant challenges for designers, including increased design rule complexity, additional layers of interconnect and the need for the use of double-pattern lithography to produce them. Synopsys estimates that it takes about three times more effort to do a custom designed circuit with FinFETs than it would take to do an equivalent planar circuit, according to Dave Reed, director of marketing for Synopsys’ analog/mixed-signal design tool group.
”FinFET brings a significant challenge to custom design,” Reed said in an interview with EE Times.
Synopsys claims that the new tool, Custom Compiler, can reduce many tasks associated with custom design from days to a matter of hours. The tool is also said to reduce iterations of designs and help enable reuse.
According to Reed, Synopsys first became fully aware of the challenges posed by custom designs with FinFETs from the company’s team of intellectual property developers. “The nice thing about these folks is that because they are doing IP development, they are among the very earliest users of new nodes,” Reed said. “We have been doing a lot together, learning how to improve custom layout for FinFET designs.”
Custom Compiler bucks the trend in custom analog design tools of moving toward constraint-driven design methodologies. Rather than require designers to write code or constraints, Custom Compiler uses what Reed calls a visually-based, successive refinement approach.
”Visually assisted automation uses the natural language of a layout person, which is graphic manipulation,” Reed said. “We don’t make them write constraints, we don’t make them write code, and we don’t try to automate something by writing a complex array generator. Instead, we do our best to infer constraints from the work that the layout person is doing.”
Synopsys believes that constraint-based design has some real flaws that have prevented it from taking off, Reed said. While the idea behind the methodology makes sense for digital designs, he added.