Tabula confirms move to Intel's 22nm process featuring 3-D tri-gate transistors

February 22, 2012 // By Julien Happich
Tabula confirmed previous speculation that it is implementing a family of 3PLD products manufactured by Intel using its advanced 22nm manufacturing process featuring 3-D Tri-Gate transistors and co-optimized packaging technology. This is made possible by a manufacturing access agreement between Tabula and Intel Custom Foundry, a division of the Technology and Manufacturing Group of Intel Corporation.

The 3PLD family will be based on Tabula's 3D Spacetime architecture and will deliver high-performance, cost-effective solutions for network infrastructure systems requiring high- bandwidth data flows such as Switches, Routers, Packet Inspection appliances, and other high-performance systems. The combination of process and architecture will allow Tabula to produce high-performance programmable circuits that consume significantly less chip area than circuits implemented with traditional FPGA fabrics.

At this week’s Ethernet Technology Summit, Daniel Gitlin, Tabula’s Vice President of Manufacturing Technology, and a veteran in PLD advanced process technology, will discuss Tabula’s approach to overcoming the limitations FPGA technologies have reached in supporting the explosive growth of bandwidth. The Summit will take place at the Doubletree hotel in San Jose, California. Mr. Gitlin will participate in the Ethernet Chipsets session (1-103), an executive panel discussion focusing on the latest advances in Ethernet technology, particularly in 40/100 GbE. The session starts at 3:10pm on Wednesday, February 22nd.

“Intel’s revolutionary manufacturing technology breakthrough employing 3-D Tri-Gate transistors at the 22nm process node will provide our company with a head start of several years, much as Intel achieved in 2007 by introducing high-k metal-gate (HKMG) transistors at the 45nm node.” said Daniel Gitlin. “We believe this breakthrough will extend Tabula’s Spacetime technology lead further beyond the rest of the programmable logic industry.”

Reducing interconnect by building 3D programmable logic devices

In traditional FPGA fabrics, interconnect is the biggest challenge since the complex circuits designers want to implement demand minimal internal delays and higher and higher operating frequencies. As FPGAs have become larger, and with the advent of 100 Gigabit Ethernet requirements, the traditional FPGAs are reaching their performance limits and bottlenecks are appearing when data moves between memory and I/O ports, and in DSP and logic functions. Eliminating these limitations, Tabula’s novel Spacetime programmable fabric delivers a balanced architecture with dramatically shorter interconnects than traditional FPGAs and the ability to clock the entire fabric – logic,