Tabula confirms move to Intel’s 22nm process featuring 3-D tri-gate transistors
The 3PLD family will be based on Tabula’s 3D Spacetime architecture and will deliver high-performance, cost-effective solutions for network infrastructure systems requiring high- bandwidth data flows such as Switches, Routers, Packet Inspection appliances, and other high-performance systems. The combination of process and architecture will allow Tabula to produce high-performance programmable circuits that consume significantly less chip area than circuits implemented with traditional FPGA fabrics.
At this week’s Ethernet Technology Summit, Daniel Gitlin, Tabula’s Vice President of Manufacturing Technology, and a veteran in PLD advanced process technology, will discuss Tabula’s approach to overcoming the limitations FPGA technologies have reached in supporting the explosive growth of bandwidth. The Summit will take place at the Doubletree hotel in San Jose, California. Mr. Gitlin will participate in the Ethernet Chipsets session (1-103), an executive panel discussion focusing on the latest advances in Ethernet technology, particularly in 40/100 GbE. The session starts at 3:10pm on Wednesday, February 22nd.
“Intel’s revolutionary manufacturing technology breakthrough employing 3-D Tri-Gate transistors at the 22nm process node will provide our company with a head start of several years, much as Intel achieved in 2007 by introducing high-k metal-gate (HKMG) transistors at the 45nm node.” said Daniel Gitlin. “We believe this breakthrough will extend Tabula’s Spacetime technology lead further beyond the rest of the programmable logic industry.”
Reducing interconnect by building 3D programmable logic devices
In traditional FPGA fabrics, interconnect is the biggest challenge since the complex circuits designers want to implement demand minimal internal delays and higher and higher operating frequencies. As FPGAs have become larger, and with the advent of 100 Gigabit Ethernet requirements, the traditional FPGAs are reaching their performance limits and bottlenecks are appearing when data moves between memory and I/O ports, and in DSP and logic functions. Eliminating these limitations, Tabula’s novel Spacetime programmable fabric delivers a balanced architecture with dramatically shorter interconnects than traditional FPGAs and the ability to clock the entire fabric – logic, DSP, memory, and interconnect — at the same frequency. To do that, the Spacetime architecture uses time as a third dimension to reduce the number of components needed to implement a function and can thus deliver smaller, higher performance, more cost-effective chips that are well suited for a wide range of applications, spanning telecommunications, enterprise networking, and wireless infrastructure markets.
“Intel’s 3-D TriGate transistors are a revolutionary breakthrough and provide an unprecedented combination of improved performance and energy efficiency, which Intel and our manufacturing customers like Tabula can use to bring superior computing capabilities to market. Intel has worked closely with Tabula throughout the product design cycle to co-optimize Tabula’s 3PLD family with Intel’s 22nm manufacturing process and design kits,” said Sunit Rikhi, vice president, Technology and Manufacturing Group, Intel.
By leveraging Intel’s 22nm process and functional enhancements to the Spacetime architecture introduced in its ABAX family, Tabula’s 22nm products will be able to meet the needs of even more complex and higher performance systems. “Tabula’s mission is to deliver the benefits of programmable logic beyond the limits of FPGAs and into the much larger $110B custom logic market.” said Dennis Segers, Tabula’s Chief Executive Officer. “This manufacturing agreement lets Tabula deliver to our customers world class process technology, coupled with large-scale manufacturing, and an advanced programmable logic fabric – all critical in our quest to grow as an independent programmable logic leader.”
Currently in volume production, the ABAX family from Tabula employs a 40-nm process and can operate at clock speeds of 1.6 GHz. The Spacetime 3D programmable logic architecture developed for the ABAX family represented a radical departure from the standard FPGA fabric approach and delivered a higher performance, more cost- effective solution. Additionally, the design flow closely resembles that of FPGAs and ASICs, using synthesis, placement, and routing tools to compile designs from RTL into silicon. Thus designers have a minimal learning curve to move their designs onto Tabula’s programmable fabric.
Visit Tabula at www.tabula.com
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