For further customization of the hub, all its descriptors can be configured to the designer’s liking. Thanks to its customizable architecture the hub can be provided in three versions: as a bare version with repeater-enhanced UTMI+ outputs, as a digital PHY enabled IP with pre-configured upstream and downstream UTMI PHY digital logic or as a complete, standalone hub targeted for particular technology together with the Evatronix’ USBHS-PHY.
The Low Power Management (LPM) feature secures the hub's compatibility with the USB 3.0 specification and thus enables designers to include the hub in the USB 3.0 hub IP as a part responsible for High, Full, and Low Speed transfers. For immediate prototyping, a proprietary board can be delivered with test chip PHYs. With its CPU-less architecture, the design is ready for verification and testing in developer’s environment right out of the box.
Visit Evatronix at www.evatronix.com/ip