UVM is becoming an industry standard approach to ensuring the reusability and interoperability of testbench code (also referred to as verification IP), integrated from multiple sources or developed using different methodologies. The Verdi UVM capabilities are enabled within the system's unified testbench and design debug environment for more efficient recording and viewing of transaction data, beyond what is supported by the current UVM infrastructure.
With the ability to visualize a broader range of information between the testbench and design under test at the transaction level, Verdi users have a more complete picture of their environment, which is especially critical during detailed regression testing phases. SpringSoft implemented full UVM source code support with the industry standard SystemVerilog library. In addition, the company provides a custom SystemVerilog file in the Verdi system to transparently record all UVM transactions into the company’s defacto standard Fast Signal Database (FSDB) for a complete record of the traffic between testbench components.
The transaction data can be used within the existing Verdi waveform tool or in a new Unified Modeling Language (UML)-based sequence diagram view. The automated mechanism eliminates the need for manual recording processes, such as the output of transactions as text messages and instrumentation of testbenches to print transactions into a text file.
Key features of the new UVM testbench debug capabilities include a tabular spreadsheet view for highlighting and filtering the transactions, easy-to-use class browsers for navigating testbench hierarchy, and automated tracing through source code to identify the origin of testbench problems. As UVM use models continue to evolve and gain broad industry adoption, SpringSoft will extend its Verdi support with dynamic data dumping capabilities as well as more advanced automation to record different kinds of data and create additional views.
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